The present invention relates to a method and /or architecture for macro-cell flip-flops generally and, more particularly, to a method and/or architecture for a macro-cell flip-flop with a scan-in input.
A programmable logic device (PLD) provides an economical and efficient means for implementing predetermined Boolean logic functions in an integrated circuit. Such a device consists of, generally, an AND plane configured to generate predetermined product terms in response to a plurality of inputs, a group of fixed/programmable OR gates configured to generate a plurality of sum-of-products(SOP) terms in response to the product terms, and a number of logic elements (i.e., macro-cells) configured to generate a desired output in response to the sum-of-products terms. The output of the macro-cells may be presented at an I/O pin or routed back to the AND plane. The sum-of-products terms can also be generated using programmable NOR-NOR or NAND-NAND logic.
Each macro-cell can contain a flip-flop called a macro-cell flip-flop. Testing the functionality of the macro-cell and surrounding logic is required. Scan test procedures are conducted to test the macro-cells and surrounding logic without increasing the device pin count. One such scan test procedure is an IEEE std 1149.1 JTAG (referred to herein as JTAG) boundary scan test. A JTAG boundary scan test is conducted with JTAG test instrumentation connected to I/O pins of the PLD.
Referring to FIG. 1, a block diagram of a conventional PLD 10 is shown. The PLD 10 has a number of macro-cells 12a-12n. Each of the macro-cells 12a-12n may be associated with an I/O pin 14a-14n. Each macro-cell has three boundary scan registers 16a-16n and an associated macro-cell flip-flop 18a-18n. Test data is shifted in and out of the flip-flops 18a-18n of each macro-cell 12a-12n using the scan registers 16a-16n. The conventional method of testing a PLD requires either a direct connection of the macro-cells 12a-12n to I/O pins 14a-14n and/or additional boundary scan registers 16a-16n. Since three boundary scan registers 16a-16n are used for each macro-cell flip-flop 18a-18n, three clock cycles are required for each test data bit to be shifted through each macro-cell 12a-12n. 
Modern PLDs continue to increase in complexity. The increasing complexity causes increased difficulty in providing direct access to the content of each macro-cell from a dedicated I/O pin. For example, a modern PLD can have, in one example, over 1500 macro-cells but less than 500 I/O pins. A solution that provides a scan chain made up of all the macro-cells of a PLD with a minimum number of I/O pins would be desirable. A solution that can use the available flip-flop resource of a macro-cell, without requiring additional boundary scan registers would also be desirable.
The present invention concerns a programmable logic device comprising a macro-cell flip-flop configured to store (i) a first input when the programmable logic device is in a normal mode and (ii) a second input when the programmable logic device is in a test mode.
The objects, features and advantages of the present invention include providing a method and/or architecture for a macro-cell flip-flop with a scan-in input that may (i) provide an easily accessible internal scan test interface, (ii) improve testability of the macro-cells and surrounding logic inside a PLD, (iii) eliminate the requirement for a one-to-one correspondence between I/O pins and macro-cells, (iv) be configured as a part of regular logic or a test scan chain, (v) easily form a test scan chain, containing all the macro-cells of a PLD, (vi) not require additional registers for a scan operation, and/or (vii) be asynchronously reset or preset.